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Beyond Compute - Where AI Hardware Creates Its Next Opportunities
The rapid expansion of artificial intelligence is driving investment not only in processing capacity but also in system-level AI hardware that enables more efficient computing performance. According to the International Energy Agency (IEA, 2026), combined capital expenditure by five major technology companies - Alphabet, Amazon, Microsoft, Meta, and Oracle exceeded US$400 billion in 2025 and was projected to increase by a further 75% in 2026. Meanwhile, the capacity of data centres specifically designed for AI more than tripled within 18 months, reflecting the scale of physical infrastructure expansion.
As AI workloads grow, system performance increasingly depends on how computing components operate together. Deloitte (2026) highlights the importance of chip- and system-level integration across compute, memory, and connectivity. This article focuses on three interconnected areas of AI semiconductor technology:
High-bandwidth memory (HBM), advanced packaging, and custom silicon.
High-Bandwidth Memory (HBM): Enabling faster data access for AI processors.
Advanced Packaging: Integrating multiple chips to improve system performance.
Custom Silicon: Optimising chip architectures for specific AI workloads.
Each addresses a distinct requirement in AI computing, from memory bandwidth and chip integration to workload-specific processing efficiency. These areas, have been highlighted in Bain & Company's 2026 technology report, represent important developments in the broader AI hardware ecosystem However, expanding demand does not guarantee commercial success, as each presents distinct manufacturing, qualification, and development constraints.
However, strong market growth does not necessarily translate into attractive returns for individual suppliers. Differences in manufacturing complexity, customer qualification, capital requirements, and contractual relationships can significantly influence commercial outcomes. This article examines four dimensions of these opportunities: market growth across the three technology areas, constraints affecting their commercialisation and scale, strategies for building competitive advantage, and how the economic benefits of AI hardware growth are distributed across the semiconductor value chain.
1. Where Is Growth Emerging in AI Semiconductors?
AI infrastructure investment is accelerating growth across specialised semiconductor technologies. According to Bain & Company (2026), high-bandwidth memory (HBM), advanced packaging, and custom silicon are among the industry's fastest-growing segments. This momentum is reflected in their revenue outlooks. Bain & Company (2026), projects HBM revenue to increase from US$4 billion in 2023 to US$106 billion by 2027, representing more than a 26-fold expansion.
Yole Group (2026) forecasts 27% CAGR for high-end performance packaging from 2025 to 2031.
While according to TrendForce (2026), servers powered by application-specific integrated circuits (ASICs) are expected to account for 27.8% of global AI server shipments in 2026, with shipment growth outpacing GPU-based systems.
These developments reflect distinct demand drivers within AI infrastructure. HBM benefits from increasing memory requirements, advanced packaging from demand for higher-density chip integration, and custom silicon from the adoption of workload-specific architectures by hyperscalers. However, growth also introduces manufacturing constraints, with limited HBM capacity, specialised packaging processes, and concentrated foundry supply affecting production scalability.
While all three areas benefit from growing AI infrastructure demand, they occupy different positions in the semiconductor value chain and face different conditions for commercial growth.
2. What Are the Key Barriers to Commercialisation?
Despite strong demand, suppliers in these three areas face different commercialisation challenges: production efficiency and qualification in HBM, manufacturing integration and capacity constraints in advanced packaging, and development cost recovery in custom silicon. According to TrendForce (2026) and Bain & Company (2026), the expansion of high-bandwidth memory (HBM), advanced packaging, and custom silicon is accompanied by distinct constraints involving accelerator-specific qualification, specialised manufacturing capacity, and the economics of custom-chip development.
HBM: Stacking complexity and accelerator-specific qualification.
HBM manufacturing requires substantially more silicon and more complex assembly than conventional dynamic random-access memory (DRAM). At Hot Chips 2026, Micron indicated that HBM requires approximately three times the wafer area of fifth-generation Double Data Rate (DDR5) memory for equivalent memory capacity, limiting output from available fabrication capacity. Customer specifications introduce additional barriers: TrendForce (2026) reported that NVIDIA's increase in fourth-generation high-bandwidth memory (HBM4) speed requirements to above 11 gigabits per second (Gbps) per pin required all three major suppliers to revise their designs and resubmit samples. Consequently, capturing demand depends on both efficient production and timely qualification for specific accelerator platforms.
Advanced packaging: Multichip integration and capacity bottlenecks.
Integrating logic dies and HBM stacks through technologies such as Chip-on-Wafer-on-Substrate (CoWoS) requires specialised interposers, substrates, bonding processes, and testing capabilities. According to TrendForce (2026), CoWoS shortages have extended across equipment and packaging materials, with Taiwan Semiconductor Manufacturing Company (TSMC) planning to expand capacity by over 60% by 2027. However, additional capacity does not automatically resolve limitations across interconnected production stages. Suppliers must secure access to critical materials and processes while achieving reliable package-level yields, making manufacturing integration and capacity availability decisive factors in commercial scalability.
Custom silicon: Design economics and workload concentration.
Unlike general-purpose accelerators, custom application-specific integrated circuits (ASICs) require substantial upfront investment justified by specific workloads and deployment volumes. The Center for Strategic and International Studies (2026) cites an estimated US$725 million development cost for a leading-edge 2-nanometer (2nm) chip, illustrating the potential scale of frontier-node investment. While this figure is not representative of all custom ASIC designs, it illustrates the substantial investment required at the technological frontier. Bain & Company (2026) identifies large, relatively homogeneous workloads as critical to amortising these costs. Commercial viability therefore depends on sufficient deployment scale and sustained cost-performance advantages over commercially available alternatives.
3. What Differentiates AI Hardware Suppliers?
The barriers discussed above can limit market entry, but they do not necessarily create a competitive advantage for every supplier. Their commercial significance depends on whether individual companies possess capabilities that customers cannot easily replace. According to Bain & Company (2026), closer memory–logic integration is increasing supplier switching barriers, while large-scale workloads are improving custom silicon economics. Meanwhile, McKinsey (2023) identifies specialised manufacturing expertise and customer co-development as differentiators in advanced packaging. These findings suggest that competitive advantage can emerge from capabilities developed to overcome segment-specific constraints.
HBM: Customer Integration and Switching Barriers.
Bain (2026) finds that co-development between memory suppliers and accelerator designers makes HBM sourcing less interchangeable than conventional memory. Early design involvement, reliable production, and repeated qualification can therefore strengthen customer relationships and increase replacement barriers.
Advanced Packaging: Manufacturing Expertise and System Integration.
McKinsey (2023) identifies specialised production expertise and integrated packaging solutions as sources of differentiation. Illustrating customer-backed capacity development, NVIDIA (2026) announced plans with Amkor to increase interposer wafer capacity by more than 300% by 2028. This partnership illustrates how major customers are supporting packaging capacity expansion, although its implications for suppliers' long-term profitability remain uncertain
Custom Silicon: Workload Specialisation and Design Efficiency.
Bain (2026) identifies large-scale, homogeneous workloads as central to custom-chip economics. Workload-specific architectures, reusable intellectual property, and design partnerships can help suppliers differentiate while reducing repeated development effort.
4. Who Captures the Economic Benefits of AI Hardware Growth?
Growth in AI hardware can improve computing efficiency and reduce costs for customers. However, these benefits do not necessarily translate into higher profitability for suppliers. The economic outcomes depend on pricing arrangements, production costs, and how financial benefits are distributed across the semiconductor value chain.
In HBM, strong demand does not always lead to higher margins. TrendForce (2026) reported that HBM profitability per wafer fell below that of conventional DDR5 memory in Q1 2026, partly because annual contracts limited suppliers' ability to adjust prices. This highlights the importance of production costs and contract terms in determining supplier profitability, even during periods of market growth.
In advanced packaging, cost savings at the chip level do not necessarily translate into higher earnings for packaging suppliers. BCG (2024) cites AMD's use of multichip architectures as an example of manufacturing cost reductions of up to 50%. However, this figure reflects savings in a specific chip design rather than the profitability of packaging providers. Their financial outcomes depend on the revenues received relative to equipment investments, operating costs, and capacity utilisation.
In custom silicon, workload-specific chips can reduce computing costs for customers, but commercial returns depend on how development expenses and financial benefits are allocated. As Bain & Company (2026) notes, sufficient deployment scale is important for recovering upfront design costs. For suppliers, profitability also depends on contractual arrangements, committed production volumes, and the revenue generated over a chip's commercial lifetime.
Across these three areas, market growth alone provides an incomplete picture of supplier profitability. The key consideration is how much of the economic benefit generated by AI hardware improvements individual businesses can retain after accounting for their costs and capital commitments.
References:
Bain & Company. (2026). Hardware strikes back in the AI era. https://www.bain.com/insights/hardware-strikes-back-in-the-ai-era-technology-report-2026/
Center for Strategic and International Studies. (2026). Innovation lightbulb: The billion-dollar chip: Who can afford to design the future? https://www.csis.org/analysis/innovation-lightbulb-billion-dollar-chip-who-can-afford-design-future
Deloitte. (2026). 2026 global semiconductor industry outlook. https://www.deloitte.com/us/en/insights/industry/technology/technology-media-telecom-outlooks/semiconductor-industry-outlook.html
McKinsey & Company. (2023). Advanced chip packaging: How manufacturers can play to win. https://www.mckinsey.com/industries/semiconductors/our-insights/advanced-chip-packaging-how-manufacturers-can-play-to-win
McKinsey & Company. (2026). Scaling AI inference. https://www.mckinsey.com/industries/semiconductors/our-insights/scaling-ai-inference
NVIDIA. (2026). NVIDIA and supply chain partners expand capacity to accelerate AI infrastructure buildout. https://nvidianews.nvidia.com/news/nvidia-and-supply-chain-partners-expand-capacity-to-accelerate-ai-infrastructure-buildout/
Tom's Hardware. (2026). Hot Chips 2026: Micron warns HBM wafer penalty is widening with every generation—AI memory uses 3x more silicon than DDR5, company says memory wall is 'getting worse' as prices rise. https://www.tomshardware.com/tech-industry/semiconductors/micron-says-the-silicon-gap-between-hbm-and-ddr5-is-widening-with-every-generation
TrendForce. (2026). AI competition turns into a supply chain arms race, tightening advanced packaging and 3nm capacity, says TrendForce. https://www.trendforce.com/presscenter/news/20260430-13028.html
TrendForce. (2026). Global AI server shipments forecast to grow over 28% YoY in 2026, with a rising share of ASIC-based systems, says TrendForce. https://www.trendforce.com/presscenter/news/20260120-12887.html
TrendForce. (2026). HBM4 mass production delayed to end of 1Q26 by spec upgrades and Nvidia strategy adjustments, says TrendForce. https://www.trendforce.com/presscenter/news/20260108-12869.html
TrendForce. (2026). Tight DRAM supply gives suppliers greater pricing power in HBM, with HBM contract prices expected to surge multiples higher in 2027, says TrendForce. https://www.trendforce.com/presscenter/news/20260602-13074.html
